Multivalued Logic Circuit Based on a Bilayer Graphene Resonant Tunneling Transistor

As electronic device scaling approaches its physical limit, multivalued logic has emerged as a promising alternative to traditional binary logic because it can significantly enhance the information processing capability of integrated circuits. Two-dimensional materials, with their dangling-bond-free surfaces, exhibit exceptional performance even at atomic thickness and are considered potential replacements for silicon in future semiconductor manufacturing processes. Multivalued logic circuits leveraging two-dimensional materials, such as ternary inverters utilizing double negative differential resistance (NDR) characteristics, have been successfully demonstrated. However, previous implementations of double NDR characteristics required two (single) NDR devices connected in series or parallel, limiting their ability to fully exploit multivalued logic for processing more information with fewer devices. In this study, a bilayer graphene resonant tunneling transistor was fabricated, which achieved double NDR characteristics by utilizing the double subbands of bilayer graphene in reciprocal space, eliminating the need for multiple devices in real space. Additionally, a MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field-effect transistor with graphene-based contacts and gate was fabricated and integrated with the resonant tunneling transistor to construct a ternary inverter. This configuration successfully implemented a ternary logic function using only two transistors, showcasing an efficient multivalued logic approach.