Extreme EOT Scaling in Tungsten-Doped In ₂ O ₃ MOSFETs for Enhanced Stability and Drive Current

Gate oxide scaling is essential for enhancing the performance of amorphous oxide semiconductor (AOS) field-effect transistors, yet it remains limited by charge trapping and interface quality. In this work, we demonstrate tungsten-doped In<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> indium–tungsten oxide (IWO) MOSFETs incorporating an amorphous HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>/ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>/HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZH) trilayer gate dielectric that achieves an equivalent oxide thickness (EOT) as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\unicode{0x00C5}$</tex-math> </inline-formula>. The transistors exhibit near-ideal subthreshold swing (SS) (75 mV/decade), high <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gt 240~{\mu }$</tex-math> </inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m), and suppressed gate leakage even at this extreme limit of EOT scaling. Positive bias-stress (PBS) tests reveal improved reliability in HZH compared with conventional HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>, with minimal threshold voltage shift. Through density-gradient-based numerical modeling and analytical stress-recovery simulations, we show that these improvements originate from spatial and energetic redistribution of oxygen vacancy induced traps into the ZrO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>-rich region, away from the channel interface. The consequent reduction in the density of acceptor-like subgap states collectively improves carrier mobility and mitigates trap-limited conduction (TLC). These results highlight the potential of targeted gate-stack engineering in extending conventional EOT scaling benefits to AOS transistors.