Universality of Subthreshold Slope and Defect Characterization in Thin Body Transistors

During the fabrication and operation of field-effect transistors (FETs), various stresses generate traps at the dielectric/channel interface and within the bulk material, leading to performance degradation, including increased subthreshold swing (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</i>) and reduced <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on-off</sub>. In this work, we (i) present a universal temperature-scaling principle for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</i>, validated across multiple thin-body transistor technologies, capturing the full temperature dependence including low-temperature saturation and high-temperature exponential behavior, and (ii) develop a closed-form analytical model that directly extracts the interface trap density from <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS(T)</i> measurements. Model predictions are validated through low-frequency noise (LFN) measurements, demonstrating excellent agreement with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS(T)</i>-extracted trap-density. The proposed framework offers a compact and scalable approach for interface trap evaluation across diverse thin-body transistor platforms.