Design of ternary logic gates based on graphene–<i>MoS</i> ₂ heterostructure

Abstract This paper presents a ternary Dirac source field-effect transistor (DS-FET) based on a graphene– MoS 2 heterostructure, designed to implement ternary logic gates with improved area and energy efficiency. The structure leverages the modulation of the graphene source’s density of states (DOS), creating intermediate states that enable the realization of three distinct logic levels essential for ternary logic. By modulating the doping levels in the graphene source region, the three types of inverter, i.e., standard ternary inverter (STI), negative ternary inverters (NTI), and positive ternary inverter (PTI) can be realized. A separate gate has been considered to induce doping in the graphene layer. A simulation framework based on the nonequilibrium Green’s function (NEGF) formalism, coupled with an atomistic tight-binding (TB) model, is utilized, with the TB parameters derived by fitting the band structure to first-principles results. The proposed DS-FET-based ternary inverter exhibits significant advantages over previous ternary logic designs in terms of static power consumption, chip area, and noise margin. In addition to the inverter, ternary NAND and NOR logic gates have also been designed using proposed DS-FET, and their transient responses have been analyzed. This work highlights the potential of graphene– MoS 2 heterostructures for developing scalable, energy-efficient ternary logic circuits and advancing the design of atomic-scale nanoelectronic devices.