Comparing the Average Delay and Power Consumption of Decoders Using Pass Transistor, Pseudo-NMOS, and Static CMOS in 45nm Technology

The comparative study of the average delay and power consumption of the 1:2 Decoder implemented using three different logic families: pass transistor logic, pseudo-NMOS, and static CMOS. The design simulated with Cadence Virtuoso using 45 nm technology demonstrates the importance of optimizing circuit components for efficient performance. Among the three configurations, the pass-transistor logic-based Decoder achieved more delay and power. Decoders play a crucial role in digital circuits, particularly in memory systems, by translating binary inputs into specific control signals. The study focuses on analyzing the trade-offs in performance metrics, specifically the average delay and power consumption, which are critical factors in modern low-power, high-performance applications.