Effect of Gate Bias and Channel Length on Total Dose Effect in FinFET Bulk Silicon Devices

FinFET devices, characterized by low static power consumption and superior switching capabilities, represent the mainstream architecture for process nodes below 22 nm. However, under radiation exposure, these devices experience degradation in electrical parameters and performance. To investigate the mechanisms and influencing factors of total ionizing dose (TID) effects, this study employs TCAD simulations to analyze the impact of gate bias and gate length on TID response in $\mathbf{1 4 ~ n m}$ bulk silicon FinFET devices, systematically examining the evolution of threshold voltage and off-state leakage current with radiation dose under varying bias conditions and channel lengths. Results demonstrate that under ON or DIODE bias conditions, the threshold voltage decreases while subthreshold swing and leakage current increase, accompanied by reduced saturation current; conversely, applying positive or negative gate bias elevates threshold voltage, suppresses subthreshold swing and leakage current, and enhances saturation current. Regarding channel length variations, short-channel devices exhibit the most significant threshold voltage and leakage current shifts, whereas long-channel devices show minimal threshold voltage and leakage current variations but the largest saturation current degradation. These findings offer guidance for optimizing FinFET design and enhancing radiation tolerance.