Development of Power-Efficient 4-Bit Arithmetic Logic Unit Using PD-RBB

The Arithmetic Logic Unit (ALU) is a critical component in digital circuits, responsible for executing arithmetic and logical operations. Hence the performance enhancement of digital circuits with a power-efficient ALU is very much important. This paper focuses on Design and development of an optimized 4-bit ALU using Pareto Distribution Reverse Body Biasing (PD-RBB) method. Here, by considering the minimum power loss, the delay is rejected. Also, the photoresist thickness fluctuations are detected by employing Bernstein Polynomial Sigmoid Fuzzy Inference System (BPS-FIS). If photoresist thickness fluctuation is present, then it is mitigated based on PD-RBB. Similarly, by using BPS-FIS, leakage current and transistor failure are detected. The Sigmoid-based Correction Non-Restoring Division (SbC-NRD) is used to perform the complex division modules in ALU operations. The Carry Look Ahead Adder (CLAA) is used to facilitate multiple operations within the ALU. Results shows that, the proposed method achieved a high leakage current reduction of 92% and a sensitivity of 98mV/V.