Design and Implementation of Sequential Element Based on CNTFET Using Multi-Threshold Style for Low Power and High-Performance VLSI Architectures

As CMOS technology nears its scaling limits, Carbon Nanotube Field Effect Transistors (CNTFETs) have emerged as a promising alternative due to their tremendous electrical properties, along with high carrier mobility and scalability. This work showcases the design and implementation of a CNTFET-based D Flip-Flop targeting low power and high performance in advanced VLSI architectures. A simple CNTFET-based D Flip-Flop is first analyzed for propagation delay and power consumption. To elevate performance, the Multiple Threshold Voltage (Multi-Vt) style is carried out through fine-tuning CN-FET chirality, optimizing the power-delay trade-off. Additionally, Sleep Transistor (ST) approach reduces leakage during idle periods of the anticipated design. The final hybrid design combines each of these techniques, displaying significatnt reduction in power consumption while preserving low delay, demonstrating the capability of CNTFETs with Multi-Vt and power gating for subsequent-generation low-energy, high-velocity sequential circuits.