Delay Insensitive Serial Register File with Limited Area

Although third-generation semiconductor technology offers significant advantages, its circuit design faces challenges of large delay variations and high stability requirements. To ensure reliable operation, delay-insensitive design methodologies are essential, particularly for Microcontroller Units (MCUs) in area-constrained applications. The General Register File (GRF), a core storage component, typically consumes substantial resources, with its parallel implementation struggling to meet area constraints due to extensive peripheral data selection circuits. This is especially problematic in resource-limited, cost-sensitive third-generation semiconductor applications. This paper presents a serial delay-insensitive GRF solution to address these area constraints. Experimental results demonstrate that our DI-Latch-based fully serial GRF design reduces LUT resource usage by 72% on FPGA implementations and decreases area by 69% in the UMC110 process compared to traditional DI-parallel designs. Similarly, the SR-Latch-based fully serial design achieves 47% reduction in LUT resources on FPGA and 25% area reduction in the UMC110 process compared to its parallel counterpart.