Design-Technology Co-Optimization and Statistical Process Variation Analysis of Complementary GAAFETs-Based Full Adder Circuits

This paper presents a comprehensive designtechnology co-optimization (DTCO) framework for complement tary gate-all-around field-effect transistors (GAAFETs)-based full adder circuits. We proposed a physics-based compact model to accurately capture the gate capacitance and drain current characteristics of GAAFETs, facilitating efficient circuit-level simulation through Verilog-A implementation. Leveraging this model, a complementary GAAFETs-based full adder circuit is achieved and validated by using Cadence Virtuoso simulation tools. Additionally, assisted with Monte Carlo method, we also investigate the impact of process variation on circuit performance fluctuations. Specifically, we considered gate length (L), nanowire channel thickness ($T_{C H}$), gate oxide thickness ($T_{O X}$) and their coupling effect on the propagation delay of the full adder circuits. The simulation results highlight critical variability parameters and demonstrate the effectiveness of our DTCO framework in guiding emerging robust nanoscale circuit designs.