FPGA Implementation of Robust Neural Network Channel Estimation for 5G and Beyond Systems

Channel estimation (CE) is an essential block in wireless communications which impacts the overall system performance. Classical CE algorithms such as minimum-mean-square-error (MMSE) CE can provide robust performance but are associated with high computational complexity. Recently, there has been growing interest in artificial intelligence (AI) native physical layer design, which will be a key component in 6G. However, designing and training a neural network (NN) for CE that can deliver robust and reliable performance in practical scenarios has proved to be a challenging task. Issues such as lack of comprehensive training dataset, large model size, power constraints, etc., have led to limited performance of NN based CE solutions compared to the classical CE methods. In this paper, a novel NN-CE method is proposed which precisely mimics robust MMSE CE functionality but with up to 55% lower computational requirements. The proposed solution does not require measured or synthetically generated channel samples for training. Efficient implementation of the proposed solution in field programmable gate array (FPGA) using parallelism and streaming techniques is explored in this paper which can further improve the speed of CE computation. Through simulations and numerical analysis, the performance and compute complexity of NN-CE is evaluated.