A Strategy for Airborne Distributed Parallel Data Transmission Based on FPGA

Airborne system is a kind of special control system, and the information exchange is one of the key technologies to ensure the stability of the control system. In order to solve the problems about complexity and variety of the cross-linking of signal in airborne system, this paper proposes a strategy for data transmission and space allocation in multiprocessor parallel bus system based on FPGA. The strategy relies on distributed control technology in multiprocessor, and uses FPGA as the data transmission node between the master processor and the slave processor. By transforming the serial transmission into parallel transmission, and the problem of bus resource sharing between the master processor and the slave processor is decoupled. In the end, we give the internal architecture of the FPGA logic, register allocation method and the process of data flow. Meanwhile, the parallel data transmission simulation is given to prove the validity of the strategy.

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Publication Details

Published
2025-06-20
DOI
https://doi.org/10.1109/isaeece66033.2025.11160194
Primary Topic
Advanced Computational Techniques and Applications
Type
article
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article

A Strategy for Airborne Distributed Parallel Data Transmission Based on FPGA

Jun Zhao, Hao Zhang, Zhiyong Zhang, Yitong Lu
Advanced Computational Techniques and Applications
article

A Strategy for Airborne Distributed Parallel Data Transmission Based on FPGA

Jun Zhao, Hao Zhang, Zhiyong Zhang, Yitong Lu
article en

Abstract

Airborne system is a kind of special control system, and the information exchange is one of the key technologies to ensure the stability of the control system. In order to solve the problems about complexity and variety of the cross-linking of signal in airborne system, this paper proposes a strategy for data transmission and space allocation in multiprocessor parallel bus system based on FPGA. The strategy relies on distributed control technology in multiprocessor, and uses FPGA as the data transmission node between the master processor and the slave processor. By transforming the serial transmission into parallel transmission, and the problem of bus resource sharing between the master processor and the slave processor is decoupled. In the end, we give the internal architecture of the FPGA logic, register allocation method and the process of data flow. Meanwhile, the parallel data transmission simulation is given to prove the validity of the strategy.

Xi'an Aeronautical University (CN)
Openalex Percentile: Top 87%
Advanced Computational Techniques and Applications
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