OptiLock: Automated Optimization of Learning-Resilient Logic Locking

Logic locking is a design-for-trust technique aiming to protect the intellectual property of integrated circuits from piracy throughout the global semiconductor supply chain. Logic locking inserts key-controlled elements (e.g., Boolean gates, referred to as key-gates) into the circuit. A secret locking key activates the functionality of the circuit, preventing unauthorized access to the design. However, the security of logic locking has been threatened by advanced machine learning-based attacks that rely solely on the structure of the locked circuit (i.e., gate-level netlist) to break logic locking and decipher the keys. Manually identifying the vulnerabilities in logic locking design, in terms of the key-gate type chosen and the location of key-gate insertion, has proven insufficient in safeguarding logic locking. Therefore, we propose OptiLock, a first-of-its-kind automated logic locking framework that supports different types of key-gates and automatically finds learning-resilient places to insert the key-gates to thwart a specific attack on logic locking, without requiring any prior knowledge of how to thwart the attack. It employs a simulated annealing algorithm in addition to customized and adjustable fitness evaluation functions that allow OptiLock to find learning-resilient logic locking solutions in terms of security and implementation overhead. OptiLock successfully thwarts four state-of-the-art attacks (MuxLink, OMLA, SCOPE, and SAAM) by optimizing the insertion of X(N)OR or multiplexer key-gates. Evaluations across ISCAS-85, ITC-99, EPFL, Ariane RISC-V benchmarks, and CVA6 RISC-V CPU design show that the proposed key-gate insertion is tailored to the original circuit structure, rather than relying on predefined locking strategies. Additionally, we demonstrate that OptiLock thwarts structural attacks such as SnapShot, Redundancy, and Resynthesis. Our evaluation further shows that OptiLock performs multi-objective optimization, achieving the desired security level while minimizing implementation costs, achieving an average delay reduction of 70.18% compared to random logic locking.