CoDAC: Algorithm-Hardware Co-Design by AutoML with Compression for Efficient Edge AI

AI at the edge demands neural networks that are simultaneously accurate, resource-efficient, and readily deployable on hardware-constrained platforms. However, the disparate optimization of algorithmic models and hardware accelerators often leads to suboptimal system performance and high deployment costs. Herein, we present CoDAC, an automated algorithm–hardware co-design framework that unifies model pruning, quantization, and hardware-oriented optimization within a closed-loop AutoML pipeline. By leveraging fast, surrogate hardware feedback and multi-objective Bayesian optimization, CoDAC efficiently explores the co-design space, achieving optimal balances among accuracy, latency, and hardware resources, tailored for FPGA accelerators. Besides, the end-to-end toolchain automates the translation of optimized, compressed models into synthesizable hardware accelerators with minimal human intervention. Evaluated on the Xilinx Zynq-7020, CoDAC achieves substantial reductions in resource usage and inference latency while maintaining competitive accuracy, yielding Pareto-optimal solutions for diverse scenarios. CoDAC highlights the effectiveness and value of co-design AutoML in optimizing lightweight models and accelerator implementations from a systemic view.