Back-Gate Bias Effects on Breakdown Voltage in Lateral Silicon-on-Insulator Power Devices

The influence of back-gate (BG) bias on the breakdown voltage (BV) of lateral SOI power devices is investigated using TCAD simulations. A reference SOI-LDMOS structure with BVREF = 73.7 V, optimized based on RESURF and charge-sharing principles, is selected as the baseline for analysis. The BV response to BG bias is shown to fall into three distinct regimes: (i) a linear decrease with increasing magnitude of negative BG bias (−65 V ≤ VG2 ≤ −5 V), (ii) an invariant region where the BV reaches its maximum value (−5 V ≤ VG2 ≤ +10 V), and (iii) a sharp reduction under increasing magnitude of positive BG bias (+10 V ≤ VG2 ≤ +65 V). Qualitative analysis of impact ionization and charge distribution confirms that inversion, depletion, and accumulation conditions in the drift region govern these behaviors. Furthermore, parametric variations in drift doping, drift thickness, and buried oxide thickness reveal significant shifts in the optimum design window, with the buried oxide thickness emerging as a critical factor for ensuring robustness of BV under BG bias. These results provide valuable design guidelines for achieving stable high-voltage performance in practical SOI-LDMOS power devices.