Method for On-line Acceleration of Dependent Operation Chains Using Redundant Code on FPGA with System of Linear Equations Example

This study examines methods for accelerating the execution of dependent operation chains in on-line mode through parallel processing of operands at the bit level in redundant code on field-programmable gate arrays (FPGA). The object of research is the hardware implementation of the Thomas algorithm for solving systems of linear equations with tridiagonal matrices on FPGA platforms. The aim is to develop a method for accelerating dependent operation chains in on-line mode using redundant code with minimization of pin count requirements. The methodology employs algorithmic analysis, hardware modeling using Active HDL, performance evaluation based on timing characteristics and resource utilization on Altera Cyclone III EP3C5E144 platform, with verification performed using Quartus. The results reveal bottlenecks in traditional FPGA implementations of the Thomas algorithm and demonstrate that the proposed optimized method provides over threefold performance improvement while maintaining constant pin count regardless of operand bit depth. The developed computing module architecture enables bit-wise parallel data processing and supports a modified version of the Thomas algorithm adapted for on-line operation. The scientific novelty lies in combining redundant code with on-line computation techniques to simultaneously achieve computational acceleration and hardware implementation simplification. The practical value is determined by the applicability of the proposed approach to resource-constrained FPGA platforms, ensuring efficient implementation of computationally intensive algorithms with dependent operation chains.