A W-Band Bidirectional Switchless PALNA in SiGe BiCMOS Technology

This paper presents an advanced W-band bidirectional Power Amplifier–Low Noise Amplifier (PALNA) implemented using 130 nm SiGe BiCMOS technology. The proposed RF front-end eliminates the need for conventional transmit/receive (T/R) switches by employing a bidirectional architecture with a passive matching network. This approach minimizes area requirements and reduces signal losses. Post-layout simulation results demonstrate that the designed PALNA achieves a peak small-signal gain of 30 dB in Tx mode and 26 dB in Rx mode, with reverse isolation better than 40 dB. The 3 dB bandwidth spans from 94 to 106 GHz. In LNA mode, the design achieves a minimum noise figure of 6 dB at 100 GHz, remaining below 6.5 dB across the entire 3 dB bandwidth. In PA mode, the simulated saturated output power is 10.5 dBm, with a maximum power-added efficiency of 12% at 100 GHz. The chip size is 0.7 mm2 including pads. It consumes 78 and 22 mW in the Tx and Rx modes, respectively.

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Publication Details

Journal
Electronics
Published
2025-09-18
DOI
https://doi.org/10.3390/electronics14183695
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

A W-Band Bidirectional Switchless PALNA in SiGe BiCMOS Technology

Bruno Barelaud, Julien Lintignat, Choayb Boudjeriou
Electronics
Radio Frequency Integrated Circuit Design
article

A W-Band Bidirectional Switchless PALNA in SiGe BiCMOS Technology

Bruno Barelaud, Julien Lintignat, Choayb Boudjeriou
article en

Abstract

This paper presents an advanced W-band bidirectional Power Amplifier–Low Noise Amplifier (PALNA) implemented using 130 nm SiGe BiCMOS technology. The proposed RF front-end eliminates the need for conventional transmit/receive (T/R) switches by employing a bidirectional architecture with a passive matching network. This approach minimizes area requirements and reduces signal losses. Post-layout simulation results demonstrate that the designed PALNA achieves a peak small-signal gain of 30 dB in Tx mode and 26 dB in Rx mode, with reverse isolation better than 40 dB. The 3 dB bandwidth spans from 94 to 106 GHz. In LNA mode, the design achieves a minimum noise figure of 6 dB at 100 GHz, remaining below 6.5 dB across the entire 3 dB bandwidth. In PA mode, the simulated saturated output power is 10.5 dBm, with a maximum power-added efficiency of 12% at 100 GHz. The chip size is 0.7 mm2 including pads. It consumes 78 and 22 mW in the Tx and Rx modes, respectively.

ElectronicsVol. 14(18)
Centre National de la Recherche Scientifique (FR), XLIM (FR), Université de Limoges (FR)
Bpifrance
Openalex Percentile: Top 75%
Radio Frequency Integrated Circuit Design
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