Multidimensional Fault Injection and Simulation Analysis for Random Number Generators

Random number generators play a critical role in ensuring information security, supporting encrypted communications, and preventing data leakage. However, the random number generators widely used in hardware are faced with potential threats such as environmental disturbances and fault injection attacks. Especially in automotive-grade environments, chips encounter threat scenarios involving multidimensional fault injection, which may lead to functional failures or malicious exploitation, endangering the security of the entire system. This paper focuses on a Counter Mode Deterministic Random Bit Generator (CTR-DRBG) based on the AES-128 algorithm and implements a hardware prototype system compliant with the NIST SP 800-22 standard on an FPGA platform. Centering on typical fault modes such as temperature disturbances, voltage glitches, electromagnetic interference, and bit flips, single-dimensional and multidimensional fault injection and simulated fault injection experiments were designed and conducted. The impact characteristics and sensitivities of electromagnetic faults, voltage faults, and temperature faults regarding the output sequences of random numbers were systematically evaluated. The experimental results show that this type of random number generator exhibits modular-level differential vulnerability under physical disturbances, especially in the data transmission processes of encryption paths and critical registers, which demonstrate higher sensitivity to flip-type faults. This research provides a feasible analysis framework and practical basis for the security assessment and fault-tolerant design of random number generators, possessing certain engineering applicability and theoretical reference value.