High-Speed Optical Neural Hardware with Adiabatic Elimination-Based ITO Logic Gates
High-speed optical logic gates are crucial for advancing photonic integrated circuits. The proposed reconfigurable ITO-based optical logic gate using adiabatic elimination demonstrates 89% speedup and 98% power reduction compared to conventional XNOR-Net implementation.
Authors
- Hamed Dalir
- Ming-Han Liao (ORCID: https://orcid.org/0000-0003-2942-4520)
- Tsai‐Fu Wu (ORCID: https://orcid.org/0000-0002-6986-6641)
- Belal Jahannia (ORCID: https://orcid.org/0009-0009-7924-3366)
- Qian Cai (ORCID: https://orcid.org/0009-0005-2486-3817)
- Chandraman Patil (ORCID: https://orcid.org/0000-0001-6362-920X)
- Jiachi Ye (ORCID: https://orcid.org/0009-0004-5370-1350)
- Hao Wang (ORCID: https://orcid.org/0000-0002-0444-6750)
- Elham Heidari (ORCID: https://orcid.org/0000-0002-8489-8094)
Publication Details
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1364/cleo_at.2025.jps100_131
- Primary Topic
- Neural Networks and Reservoir Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00