Developing spin-transfer torque (STT)-resistant stochastic MTJs for complementary metal-oxide-semiconductor (CMOS)-integrated probabilistic bits

The probabilistic bit (or p-bit, the base unit of probabilistic computing) requires tunable stochasticity, with networks of fluctuating correlated p-bits acting as efficient hardware accelerators for probabilistic algorithms. An ideal source of this stochasticity is found in magnetic tunnel junctions (MTJs) with low-barrier free layers; with the stochastic MTJ (sMTJ) providing the true random number generation and a three-transistor circuit providing the tunability and amplification, a compact implementation of a voltage-controlled p-bit is achieved. In this work, we present experimental results showing how spin-transfer torque (STT) effects can compromise the sMTJ, impairing its function as a true random number generator, and how we may engineer the oxide layer in the MTJ to create STT-resistant devices. We then show for the first time the monolithic integration of these stochastic MTJs with a CMOS tape-out using the 180nm-node technology from TSMC, demonstrating an on-chip integrated 1T-1MTJ p-bit core that can operate at the volt-level.