Advancing photonic architectures: scalability and energy efficiency for next-generation accelerators

The complexity of deep neural networks (DNNs) increased, calling for more efficient and scalable hardware accelerators. In this paper, we discuss the scalability of photonic accelerators based on a scale-out methodology and the effect of processing element (PE) grid configurations on efficiency and performance. We simulate 64 PE and 512 PE configurations of the various neural network models using an adapted version of SCALE-Sim. Our experiments illustrate that near-square or square grid partitioning (e.g., 8x8 for 64 PEs, 16x32 for 512 PEs) offers the optimum balance between utilization, execution time, and memory access efficiency. Layer-by-layer comparisons exhibit varying gains in performance across network stages, and thus static configurations could not be efficient for DNNs. While the scaleup from 64 to 512 PEs offers substantial speedup, it also does so at decreasing returns in resource utilization. These results underscore the necessity for reconfigurable photonic accelerator architectures to support layer-dependent specifications. Our research provides insights for the design of next-generation photonic accelerators with flexible and scale-out architectures to address DNN applications’ changing needs.