Towards the implementation of analog neural network architecture using conventional analog circuit configurations

Edge-Artificial Intelligence (AI) has emerged as a transformative approach to AI deployment by keeping models local to the devices collecting data, thereby enhancing data security and accelerating service. Analog electronics have been identified as a promising alternative for improving Edge-AI devices by enabling real-time sensor data processing, reducing CPU usage, and lowering power consumption, as demonstrated through in-memory analog computing. Herein, a proof-of-concept method is presented for translating neural network operations—both training and inference—into conventional analog circuits. Learning is parameterized over time, and traditional multiply-accumulate-activate neuron functions are emulated. Voltage-controlled resistors (VCRs) based on JFET transistors are employed to approximate multiplication; summation circuits are used to aggregate weighted inputs; a common-source amplifier is implemented to replicate sigmoid responses; and a voltage-bounding buffer simulates Rectified Linear Unit (ReLU) behavior. Experimental results indicate that five out of six tested networks converged within 150 ms, achieving errors below 3%, thereby validating the architecture and optimization techniques. Further research is required to assess scalability for larger networks and integration with conventional chips and semiconductor technologies. The introduced proof-of-concept may serve as a foundation for advancements in analog circuit optimization and AI hardware implementation.