Investigation of Overcurrent Turn-Off Robustness of 1200 V SiC MOSFETs

The aim of this study is to investigate the overcurrent turn-off robustness limit of SiC MOSFETs from three different manufacturers with three different cell technologies up to very high turn-off currents to determine a possible destruction limit and failure type. The influence of the negative gate-source voltage ( V GS,off ) was studied because of the high drain-source overvoltage in connection with the decreased V GS,off , which is the most critical point for the gate oxide field stress for the different cell technologies. All measurements were performed at a positive gate-source voltage ( V GS,on ) above the specified datasheet values to reach high currents without channel pinch-off. In addition, the influence of temperature on the overcurrent robustness was studied. Finally, TCAD simulations were performed to determine the reason for the failure mechanism under the overcurrent turn-off conditions. All the manufacturer devices can withstand several times higher gate-source voltages under overcurrent conditions than the values recommended in the datasheet.