A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter

This letter presents a radiation-hardened (rad-hard) sub-sampled Phase-Locked Loop (SS-PLL) that achieves state-of-the-art jitter performance while incorporating radiation-hardened techinues to mitigate single event upsets (SEUs) present in the space environment. Furthermore, rad-hard techniques are incorporated in each core PLL sub-block which include a rad-hard charge-pump Gm cell, a pulser circuit with triple modular redundancy (TMR), and a quad-core Voltage-Controlled Oscillator (VCO) with varactor hardening and LC tail filters. Implemented in a 16nm FinFET process, the PLL consumes 36.5mW of power and achieves a jitter of 45.82 fs at 19.5 GHz. Testing at a cyclotron facility verifies robust SEU performance up to an LET of 55 MeV7cm2/mg.