Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults
Advanced delay fault models such as the two-cycle defectaware, cell-aware or gate-exhaustive fault models associate faults with pairs of input patterns of gates (or cells). The large numbers of faults defined for these fault models result in large test sets. This article addresses the need to control the size of a scan-based test set for two-cycle gate-exhaustive faults in two ways: (1) only functionally possible faults, i.e., faults that can cause a circuit to fail during functional operation, contribute new tests to the test set; and (2) multicycle tests are used to increase the number of faults that each test can detect. The effectiveness of multicycle tests for advanced fault models results from the following key observation. Faults that are associated with the same gate cannot be detected by the same two-cycle test, but a multicycle test can detect several faults that are associated with the same gate by activating the faults at different clock cycles. The article describes a test compaction procedure that uses this observation, and presents experimental results for benchmark circuits in an academic simulation environment to demonstrate its effectiveness.
Authors
- Irith Pomeranz (ORCID: https://orcid.org/0000-0002-5491-7282)
Institutions
- Purdue University West Lafayette (US)
Publication Details
- Journal
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/tcad.2025.3611112
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00