Low Power High Speed Multiplier Based on Spurious Power Suppression Techniue

Abstract: A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is a key parameter while designing a multiplier for a specific Application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. Generally as we know multiplication goes in two basic steps, Partial product and then addition. Hence in this paper we have first tried to design ripple carry adder and carry select adder and compare their speed and complexity of circuit i.e. the area occupied. While comparing the adders we found out that Ripple Carry Adder had a smaller area while having lesser speed, in contrast to which Carry Select Adders are high speed but posses a larger area. The result is a completely synthesized Efficient 8-by-8 shift and adds multiplier with low power and low area compared to the low power structure called bypass zero, feed a directly (BZ-FAD) TECHNIQUE of shift-and-add multipliers. The simulation result for 8 bit multipliers shows that the proposed low power architecture lowers the total power consumption by 51.11% when compared to the conventional architecture.