P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs

The rising demand for high-bandwidth, low-latency network processing has led to a significant shift towards programmable data planes. The P4 language enables network operators to define packet processing pipelines flexibly. However, efficiently deploying P4-defined applications onto Field-Programmable Gate Arrays (FPGAs) remains a complex task due to the low-level hardware design requirements. This paper introduces P4THLS, a templated high-level synthesis framework that converts P4 data-plane applications into synthesizable C++ code for FPGA deployment. Key contributions include an automatic design process, a templated data structure and bus width, and unified memory management techniques. The proposed P4THLS architecture is evaluated through experiments, showing significant improvements in throughput, latency, and resource utilization over existing FPGA-based packet processing methods. The experiments demonstrate that P4THLS achieves up to 143.3 Gbps throughput with a 512-bit bus and 76.5 Gbps with a 256-bit bus, supports match-action tables with up to 64K entries, and sustains sub-50-cycle processing latency at 250 MHz, with end-to-end latencies of around 8 μs.