Design of Energy Efficient RFET-Based Polymorphic Logic Gates

Polymorphic gates are logic hardware components designed to have reconfigurable functionalities and perform context-dependent operations. These gates were often implemented using emerging technologies with intrinsic properties that can be exploited to alter the logical operation, such as Reconfigurable Field-Effect Transistors (RFETs). However, the majority of the proposed topologies still remain rooted in conventional design paradigms, thus only partially exploiting the benefits of such advanced devices. In this Brief, we present a universal polymorphic topology purposely conceived for RFETs that can be configured to implement any combination of 2-input logic functions and their inversions, by simply acting on external configuration signals. When realized using a 14nm process technology, the proposed gate, configured as NAND-XNOR-XOR-AND, shows a delay of 19ps and dissipates ~1.8fJ, which is nearly the same as that required by a simple XNOR gate realized using RFETs. At the parity of logic functionality, the proposed scheme leads to a reduction in delay and energy dissipation of up to 64% and 57.9%, respectively, compared to conventional approaches.