Design, Simulate, and Layout for a Static Random-Access Memory (SRAM) Using a 6T Memory Cell and a Latch-Based Sense Amplifier

This research study focuses on the implementation and assessment of a 64-bit SRAM (Static Random-Access Memory) design utilizing 6T memory cells. The objective of this SRAM design, as presented in this study, is to explore its structure, functionality, and key attributes. To achieve this, the Cadence Virtuoso tool is employed for both design implementation and evaluation, utilizing the CMOS technology library. The design incorporates 6T memory arrays, which are commonly used in modern SRAM designs, along with additional peripheral components for efficient array management. The memory circuit will be constructed using the Virtuoso Schematic Editor, and its physical layout will be created using the Virtuoso Layout Suite XL. The read and write operations are validated through timing diagrams for various scenarios. Furthermore, the stability of the 6T memory cells is ensured by conducting an SNM (Static Noise Margin) analysis. From a layout perspective, each component undergoes thorough verification for Design Rule Checking (DRC) and Layout vs. Schematic (LVS) using the Assura tool.