A Differential Series-Resonance CMOS VCO Leveraging Pole-Convergence Technique, With a General Result on Tank Phase Noise

The series-resonance (SR) oscillator topology has been proven capable of achieving ultra-low phase noise (PN) while overcoming the limitations of multi-core oscillator topologies, such as inter-core mismatch and excessive chip area. However, prior SR oscillator topologies still face various challenges, including design complexity and mode ambiguity. In this article, a novel differential SR voltage-controlled oscillator (SR-VCO) topology that leverages the pole-convergence technique is proposed, offering design simplicity and immunity to mode ambiguity, while achieving ultra-low PN with single-core implementation. An equivalent circuit model for the transformer-based tank is developed. A general result on the tank PN is derived, where the effects of active devices on the tank are considered. Also, a technique to suppress the noise contribution from the bias resistor in the switched-capacitor array (SCA) is proposed. Implemented in a 65-nm bulk CMOS process, the proposed SR-VCO achieves a PN of −152.89 dBc/Hz at 10-MHz offset from 9.122 GHz, a tuning range (TR) of 17.7% (7.65–9.135 GHz), a peak figure of merit (FoM) of 190 dBc/Hz, and an FoM for TR and area (FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub>) of 202.13 dBc/Hz at 10-MHz offset, while all devices operate within safe voltage swings.