DESIGN AND IMPLEMENTATION OF SRAM ARCHITECTURE FOR MULTISTAGE RING OSCILLATOR PUF AND READ-CURRENT DISCHARGE-BASED PUF

This research explores the design and implementation of a configurable 10-transistor (10T) SRAM architecture for enhancing the security of Physical Unclonable Functions (PUFs) in resource-constrained environments. The primary focus is to develop two PUF variants: a Multistage Ring Oscillator (RO) PUF and a read-current discharge-based entropy source PUF. The proposed SRAM architecture leverages the robustness and configurability of the 10T SRAM cell to improve the stability, reliability, and uniqueness of the generated PUF responses. This study investigates key performance metrics including uniqueness, reliability, bit error rate (BER), key error rate (KER), uniformity, stability, and randomness. Additionally, the entropy characteristics of the read-current discharge-based PUF are analyzed to assess its suitability as a source of randomness. The impact of environmental factors such as voltage and temperature variations on the PUF performance is also examined. The results show that the 10T SRAM architecture effectively enhances the stability and uniqueness of PUF responses, making it a promising candidate for low-power, secure identity generation and authentication in Internet of Things (IoT) and embedded system applications. The proposed architecture provides a viable solution for improving the reliability and efficiency of PUFs, with potential for further optimization in future work.