A Reconfigurable Variable-Precision Bipolar/Binary QR-based IMC Accelerator in 22nm FDSOI

In-memory computing (IMC) hardware is crucial for enabling low-power neural network (NN) inference on edge devices. The charge redistribution (QR) IMC compute model dominates state-of-the-art (SOTA) IMC hardware implementations. However, existing QR IMC implementations are inflexible in terms of supportable bit-precisions and weight data types. On the other hand, different NN models have been found to require different optimal bit-precisions for energy efficiency. Additionally, challenges such as V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> variations arise in deeper tech nodes. Here, we introduce a variable-precision QR-based IMC accelerator based on a 10T1C bitcell that supports both bipolar and binary weights. We achieve a maximum energy efficiency close to recent SOTA at 516 TOPS/W, 409.6 GOPS at a compute SNR of 21.03 dB.