Optimizing DSM With Predictive Coherence

In distributed shared memory (DSM) systems, maintaining coherence across multiple nodes can introduce significant latency and performance overhead. This paper explores the potential of predictive mechanisms to mitigate these challenges, specifically focusing on invalidation prediction and consumer prediction within the MESI coherence protocol. We analyze memory access patterns and their frequencies using the PARSEC 3.0 benchmark suite, which represents a range of modern shared memory workloads. Our study introduces two novel consumer predictors: the LRU Consumer Predictor and the Override Consumer Predictor. These predictors are designed to enhance the efficiency of predicting which processors will access a cache line after a write operation, thereby reducing the number of coherence messages and improving overall system performance. The LRU Consumer Predictor leverages a two-level table-based approach with a Least Recently Used (LRU) replacement policy [1], while the Override Consumer Predictor incorporates an additional Consumer History Table (CHT) to address inaccuracies in consumer prediction. Our methodology includes extensive memory trace analysis and performance evaluation on a high-performance computing cluster. The results demonstrate that predictive coherence mechanisms can significantly reduce latency and network traffic, leading to more efficient DSM operations.