A 6.4-GS/s, 200-MHz BW 77.3-dB DR 71.5-dB SNDR 2× TI Extrapolated CT DSM Employing Broadband Hybrid-Inputs Adder and Nonlinearity-Suppression DAC Encoder

This article presents a wideband two-channel (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{\times }$</tex-math> </inline-formula>) time-interleaved (TI) continuous-time (CT) delta-sigma modulator (DSM). <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{\times }$</tex-math> </inline-formula> TI technique halves the speed of the whole DSM loop. The feedforward (FF) extrapolation enables an equivalent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{\times }$</tex-math> </inline-formula> TI implementation using only one complete analog DSM channel. Moreover, a broadband hybrid-input (i.e., resistor/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula>/IDAC/CDAC) current-mode adder is proposed to implement the summing stage, which is required by the FF extrapolation and excess loop delay (ELD) compensation. To expedite the adder operation, the bandwidth (BW) of the speed-critical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula>-input paths inside the adder is extended by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.6{\times }$</tex-math> </inline-formula> by applying resistorcapacitor degenerations. Moreover, considering that the signal features of the output feedback from the two channels are similar, a preceding tri-level encoder is used for the outermost digital-to-analog converters (DACs), while both thermometer-type inputs are combined in opposite directions. It can significantly mitigate the linearity requirement of the outermost DACs. Sampled at 3.2 GHz, the 28-nm CMOS prototype achieves an equivalent sampling rate of 6.4 GHz [oversampling ratio (OSR) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${=}16$</tex-math> </inline-formula>]. It measures 77.3-dB DR, 71.5-dB SNDR, and 81.6-dB SFDR over 200-MHz BW while consuming 106-mW power. It results in state-of-the-art (SoTA) Schreier FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{S\vert \mathrm { SNDR}}$</tex-math> </inline-formula> of 164.3 dB and FoM<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{S\vert \mathrm { DR}}$</tex-math> </inline-formula> of 170.1 dB. Note that it does not employ any explicit DAC linearization techniques.