A High-Performance and Configurable NTT Accelerator Based on Scalable 2-D Architecture

The number theoretic transform (NTT), which can reduce the computational complexity of polynomial multiplication, has been widely used to accelerate cryptographic algorithms. However, due to the significant computational data volume, the limited memory bandwidth of chips limits the effectiveness of massive parallel computation in achieving high performance. In addition, the accelerator must flexibly adapt to variable parameters for diverse encryption scenarios, leading to a nonlinear growth in hardware resources and underutilization of the computation engines. Therefore, this article proposes a scalable 2-D constant-geometry (2-D CG) accelerator designed to fully utilize butterfly units (BFUs) and avoid a drastic increase in hardware resources. The proposed architecture reduces high memory bandwidth requirements by compressing BFUs from the vertical to the horizontal direction, thereby eliminating BFU idle time waiting for data transmission. We then propose a scalable 2-D CG design that performs a constant number of data access patterns within each stage to prevent the dramatic increase in complexity as the architecture scales. In addition, we propose a channel reconfigurable Barrett (CR_Barrett) architecture that computes multiple small-bitwidth modular multiplications (MMs) in parallel, ensuring that all computation engines are actively utilized. Finally, we designed and verified the proposed 2-D CG NTT accelerator on a field-programmable gate array (FPGA). Compared to state-of-the-art works, the 2-D CG achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.47\times $</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.17\times $</tex-math> </inline-formula> higher throughput per slice (TPS) for scalable architectures and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.02\times $</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.41\times $</tex-math> </inline-formula> higher TPS for runtime configurable architectures.

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Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2025-09-16
DOI
https://doi.org/10.1109/tvlsi.2025.3606636
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
0.00
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article

A High-Performance and Configurable NTT Accelerator Based on Scalable 2-D Architecture

Hao Xiao, Jianbo Guo, Jiandong Zhu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CCD and CMOS Imaging Sensors
article

A High-Performance and Configurable NTT Accelerator Based on Scalable 2-D Architecture

Hao Xiao, Jianbo Guo, Jiandong Zhu
article en

Abstract

The number theoretic transform (NTT), which can reduce the computational complexity of polynomial multiplication, has been widely used to accelerate cryptographic algorithms. However, due to the significant computational data volume, the limited memory bandwidth of chips limits the effectiveness of massive parallel computation in achieving high performance. In addition, the accelerator must flexibly adapt to variable parameters for diverse encryption scenarios, leading to a nonlinear growth in hardware resources and underutilization of the computation engines. Therefore, this article proposes a scalable 2-D constant-geometry (2-D CG) accelerator designed to fully utilize butterfly units (BFUs) and avoid a drastic increase in hardware resources. The proposed architecture reduces high memory bandwidth requirements by compressing BFUs from the vertical to the horizontal direction, thereby eliminating BFU idle time waiting for data transmission. We then propose a scalable 2-D CG design that performs a constant number of data access patterns within each stage to prevent the dramatic increase in complexity as the architecture scales. In addition, we propose a channel reconfigurable Barrett (CR_Barrett) architecture that computes multiple small-bitwidth modular multiplications (MMs) in parallel, ensuring that all computation engines are actively utilized. Finally, we designed and verified the proposed 2-D CG NTT accelerator on a field-programmable gate array (FPGA). Compared to state-of-the-art works, the 2-D CG achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.47\times $</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.17\times $</tex-math> </inline-formula> higher throughput per slice (TPS) for scalable architectures and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.02\times $</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.41\times $</tex-math> </inline-formula> higher TPS for runtime configurable architectures.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 34(2)
Hefei University of Technology (CN)
Openalex Percentile: Top 76%
CCD and CMOS Imaging Sensors
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