Harmonic Minimization in a Reduced Switch Count 17-Level Switched Capacitor Multilevel Inverter Using Hybrid Ant Colony Optimization Technique

This paper presents a 17-level high-gain switched capacitor multilevel inverter (HG-SCMLI) topology that achieves multiple voltage levels with significantly reduced component count while utilizing a single DC source. The primary innovation lies in the topology's unique configuration, which uses only 16 components to generate a 17-level output voltage with a voltage gain of 8, resulting in a low total component-to-gain ratio. The proposed HG-SCMLI addresses two critical challenges in conventional designs: excessive component count and high input inrush currents. The topology features inherent self-balancing of capacitor voltages without additional sensors, reducing control complexity. To demonstrate the topology's capability for high-quality power conversion, selective harmonic elimination pulse width modulation governed by a hybrid ant colony optimization (HACO) algorithm is implemented. An 850 W laboratory prototype with 94.50% efficiency and a peak efficiency of 95.60% at 185 W has been developed and tested under various loading conditions and modulation indices, validating the topology's practical performance.