A 700 MS/s 12-bit Pipeline-ADC With a Sub-Range 6-bit Back-End Achieving 79 dB Signal-to-Distortion Ratio and FoM of 170.1 dB Near Nyquist Frequency

This paper presents a 12-bit, 700-MS/s pipeline ADC fabricated in TSMC 40-nm technology, with a focus on power optimization in residue amplifiers and comparator cells. The effective transconductance of the inter-stage amplifiers and comparators is optimized for the minimum power consumption while meeting CDAC matching requirements. The architecture consists of two 3.5-bit/stage blocks in cascade with a sub-range 6-bits flash ADC. A two-stage class AB residue amplifier with cascode output stage and complementary differential pairs is employed, effectively double its DC gain and capable of achieving twice the slew rate (SR) and gain-bandwidth product (GBW) compared to the conventional design with equivalent power consumption. The residue amplifier does not require specific frequency compensation since the cascode output stage and large load capacitor determine the dominant pole that is naturally separated from the pole generated at the output of the first stage. To further enhance ADC’s power efficiency, the multiplying digital-to-analog converter (MDAC) of the second stage is designed to enable the functionality of the subsequent sub-range 6-bit flash ADC. The two-step 6-bit backend stage resolves the last 3 MSBs and 3 LSBs sequentially, significantly reducing power consumption. A digital calibration scheme employing key DC test signals effectively correct gain and non-linearity errors. Experimental results for a 40nm CMOS prototype show that the proposed pipeline ADC achieves a Signal-to-Noise and Distortion Ratio (SNDR) of 69.2 dB and a Spurious-Free Dynamic Range (SFDR) of 81.5 dB at low input frequencies. 68.5 dB SNDR and 80.7 dB SFDR near the Nyquist frequency at 700 MS/s are achieved. The ADC core occupies an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.56~mm^{2}$</tex-math> </inline-formula> and consumes 24.3 mW from a 1.2 V power supply. Near Nyquist frequency, the measured Schreier figure of merit is approximately 170.1 dB.

Authors

Institutions

Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-09-16
DOI
https://doi.org/10.1109/tcsi.2025.3605848
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.67
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

A 700 MS/s 12-bit Pipeline-ADC With a Sub-Range 6-bit Back-End Achieving 79 dB Signal-to-Distortion Ratio and FoM of 170.1 dB Near Nyquist Frequency

José Silva-Martínez, Martin Kinyua, Eric Soenen, Amr W. Hassan et al.
1 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Analog and Mixed-Signal Circuit Design
0.67
article

A 700 MS/s 12-bit Pipeline-ADC With a Sub-Range 6-bit Back-End Achieving 79 dB Signal-to-Distortion Ratio and FoM of 170.1 dB Near Nyquist Frequency

José Silva-Martínez, Martin Kinyua, Eric Soenen, Amr W. Hassan, Shiqiang Qiu
article en
1 citations

Abstract

This paper presents a 12-bit, 700-MS/s pipeline ADC fabricated in TSMC 40-nm technology, with a focus on power optimization in residue amplifiers and comparator cells. The effective transconductance of the inter-stage amplifiers and comparators is optimized for the minimum power consumption while meeting CDAC matching requirements. The architecture consists of two 3.5-bit/stage blocks in cascade with a sub-range 6-bits flash ADC. A two-stage class AB residue amplifier with cascode output stage and complementary differential pairs is employed, effectively double its DC gain and capable of achieving twice the slew rate (SR) and gain-bandwidth product (GBW) compared to the conventional design with equivalent power consumption. The residue amplifier does not require specific frequency compensation since the cascode output stage and large load capacitor determine the dominant pole that is naturally separated from the pole generated at the output of the first stage. To further enhance ADC’s power efficiency, the multiplying digital-to-analog converter (MDAC) of the second stage is designed to enable the functionality of the subsequent sub-range 6-bit flash ADC. The two-step 6-bit backend stage resolves the last 3 MSBs and 3 LSBs sequentially, significantly reducing power consumption. A digital calibration scheme employing key DC test signals effectively correct gain and non-linearity errors. Experimental results for a 40nm CMOS prototype show that the proposed pipeline ADC achieves a Signal-to-Noise and Distortion Ratio (SNDR) of 69.2 dB and a Spurious-Free Dynamic Range (SFDR) of 81.5 dB at low input frequencies. 68.5 dB SNDR and 80.7 dB SFDR near the Nyquist frequency at 700 MS/s are achieved. The ADC core occupies an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.56~mm^{2}$</tex-math> </inline-formula> and consumes 24.3 mW from a 1.2 V power supply. Near Nyquist frequency, the measured Schreier figure of merit is approximately 170.1 dB.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 73(3)
Taiwan Semiconductor Manufacturing Company (United States) (US), Advanced Micro Devices (United States) (US), Texas A&M University (US)
Openalex Percentile: Top 27%
Analog and Mixed-Signal Circuit Design
0.67
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.