Designs of four universal architectures for multi-valued quantum adders

Abstract Multi-valued quantum adder circuits, based on multi-valued logic, are significant components in numerous quantum algorithms. Their low-cost implementations can enhance the efficiency of these algorithms. In this paper, innovative universal architectures for d ( d >3)-level quantum half-adder, full-adder, parallel adder, and parallel adder/subtractor circuits are designed using d -level 1-qudit (quantum digit) and M–S gates. To demonstrate the effectiveness of these architectures, quaternary adder circuits derived from them are displayed and compared with several existing counterparts. Judging by the results, these circuits exhibit reductions in quantum cost (QC), hardware complexity (HC), number of constant inputs (NCIs), and number of garbage outputs (NGOs).