AutoMarks: A GNN-based Automated Physical Design Watermarking Framework

Physical design refers to converting a logical circuit description into a physical chip layout for manufacturing. Although design companies invest huge efforts to fine-tune the cell positions and connections for better power, performance, and area metrics, chip layouts are vulnerable to security risks along the supply chain. Physical design watermarking injects signatures on the chip layout, allowing ownership authentication and avoiding potential security risks. A substantial effort is required to identify the best locations to insert the watermarks on the chip layout without affecting the overall layout quality. This paper presents AutoMarks , an automated and transferable watermarking framework that leverages graph neural networks to reduce watermark search overhead during the integrated circuit design’s placement stage. AutoMarks ’s novel automated watermark search is accomplished by (i) constructing novel graph and node features with physical, semantic, and design constraint-aware representation; (ii) designing a data-efficient sampling strategy for watermarking fidelity label collection; and (iii) leveraging a graph neural network to learn the connectivity between cells and predict the watermarking fidelity on unseen layouts. Extensive evaluations on ISPD’15, ISPD’19, and ICCAD’15 benchmarks demonstrate that our proposed automated methodology: (i) is capable of finding quality-preserving watermarks in a short time; (ii) is transferable across various designs, i.e., AutoMarks trained on one layout is generalizable to other benchmark circuits; (iii) is effective in watermarking designs optimized for wirelength and timing metrics. AutoMarks is also resilient against potential watermark removal and forging attacks. Our code is publicly available on GitHub.