Invited paper: Enhancing Design Automation with Quantum Algorithms for Chip Design

The design of resource-efficient chips has become a critical priority for the semiconductor industry. A key challenge in this process is the placement of cells on the chip’s physical layout to optimize performance and manufacturability. The present work proposes a novel optimization strategy to determine cell placements that minimize the Half-Perimeter Wire Length (HPWL), a metric strongly correlated with chip area and power consumption. The presented approach is designed for flexibility, enabling integration with diverse optimization methods, and demonstrates implementations using both a custom Simulated Annealing (SA) algorithm and a D-Wave Constrained Quadratic Model (CQM) solver. The resulting placements were validated through integration with the OpenROAD flow, bridging the gap between classical, quantum, and hybrid optimization algorithms and industry standard tools for chip design and routing with a real-world case using the ASAP7 7nm PDK. Preliminary results indicate that the proposed approach provides better area usage and considerable speedup / performance improvement showing a path towards the usage of quantum computer for chip design EDA workloads.