Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization

Statistical timing characterization for standard cells faces significant computational challenges due to the laborious bisection analysis for setup/hold constraint of sequential cells. To address this issue, we propose a Bisection-Free Learning Approach for Statistical Timing Characterization (BLAST) by extracting inherent delay for data path and clock path in sequential cells as specific features. Multi-task learning is implemented with a multi-gate mixture-of-experts (MMoE) model to exploit the profound interdependency between setup and hold constraint for different timing arcs, where the active learning strategy is incorporated to improve learning efficiency. Experimental results under 135 PVT corners with TSMC 12nm process demonstrate that the proposed BLAST achieves considerable acceleration by avoiding the iterative bisection search for statistical constraint prediction with 76.9% runtime reduction compared to the commercial tool. Excellent prediction accuracy is achieved for various flip-flops by BLAST with the relative root mean square error (rRMSE) of $\mathbf{2. 2 1 \%}$ and worst-case absolute error (WCAE) of 0.82 ps.

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Published
2025-06-22
DOI
https://doi.org/10.1109/dac63849.2025.11133163
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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article

Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization

J. B. Jiao, Peng Cao, Zeyuan Deng, Kai Jing et al.
VLSI and Analog Circuit Testing
article

Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization

J. B. Jiao, Peng Cao, Zeyuan Deng, Kai Jing, Tao Bai
article en

Abstract

Statistical timing characterization for standard cells faces significant computational challenges due to the laborious bisection analysis for setup/hold constraint of sequential cells. To address this issue, we propose a Bisection-Free Learning Approach for Statistical Timing Characterization (BLAST) by extracting inherent delay for data path and clock path in sequential cells as specific features. Multi-task learning is implemented with a multi-gate mixture-of-experts (MMoE) model to exploit the profound interdependency between setup and hold constraint for different timing arcs, where the active learning strategy is incorporated to improve learning efficiency. Experimental results under 135 PVT corners with TSMC 12nm process demonstrate that the proposed BLAST achieves considerable acceleration by avoiding the iterative bisection search for statistical constraint prediction with 76.9% runtime reduction compared to the commercial tool. Excellent prediction accuracy is achieved for various flip-flops by BLAST with the relative root mean square error (rRMSE) of $\mathbf{2. 2 1 \%}$ and worst-case absolute error (WCAE) of 0.82 ps.

Southeast University (CN)
Openalex Percentile: Top 73%
VLSI and Analog Circuit Testing
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Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization — J. B. Jiao, Peng Cao, et al. · (2025) | TGRS Research Map | TGRS