April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators

Neural Networks (NNs) have achieved breakthroughs in computer vision and natural language processing. However, modern models are computationally expensive, with floating-point operations posing a major bottleneck. Floatingpoint approximation, such as Mitchell’s logarithm, enables floating-point multiplication using simpler integer additions, thereby improving hardware efficiency. However, its practical adoption is hindered by challenges such as precision degradation, efficient hardware integrations, and management of trade-offs between accuracy and resource efficiency. In this paper, we propose a hardware-efficient down-samplingbased compensation method to mitigate precision loss and a flexible bias mechanism to accommodate diverse data distributions in NN models. Building on this foundation, we design configurable systolic arrays optimized for NN accelerators. To further support practical adoption, we introduce April, a co-design framework that balances the accuracy and resource usage of generated synthesizable systolic arrays. Our FPGA-based evaluations demonstrate that April-generated systolic arrays reduce root mean square error (RMSE) by up to $\mathbf{9 6 \%}$ and achieve $\mathbf{3 4 \% -5 2 \%}$ area reduction even compared to INT8-based implementations while maintaining comparable or improved model accuracy. Our design is open-sourced at https://github.com/CLabGit/April

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Publication Details

Published
2025-06-22
DOI
https://doi.org/10.1109/dac63849.2025.11133083
Citations
3
Primary Topic
Neural Networks and Applications
Type
article
Field-Weighted Citation Impact
7.44
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article

April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators

Jiaxiang Zou, Xinyu Chen, Yonghao Chen
3 citations
Neural Networks and Applications
7.44
article

April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators

Jiaxiang Zou, Xinyu Chen, Yonghao Chen
article en
3 citations

Abstract

Neural Networks (NNs) have achieved breakthroughs in computer vision and natural language processing. However, modern models are computationally expensive, with floating-point operations posing a major bottleneck. Floatingpoint approximation, such as Mitchell’s logarithm, enables floating-point multiplication using simpler integer additions, thereby improving hardware efficiency. However, its practical adoption is hindered by challenges such as precision degradation, efficient hardware integrations, and management of trade-offs between accuracy and resource efficiency. In this paper, we propose a hardware-efficient down-samplingbased compensation method to mitigate precision loss and a flexible bias mechanism to accommodate diverse data distributions in NN models. Building on this foundation, we design configurable systolic arrays optimized for NN accelerators. To further support practical adoption, we introduce April, a co-design framework that balances the accuracy and resource usage of generated synthesizable systolic arrays. Our FPGA-based evaluations demonstrate that April-generated systolic arrays reduce root mean square error (RMSE) by up to $\mathbf{9 6 \%}$ and achieve $\mathbf{3 4 \% -5 2 \%}$ area reduction even compared to INT8-based implementations while maintaining comparable or improved model accuracy. Our design is open-sourced at https://github.com/CLabGit/April

University of Electronic Science and Technology of China (CN)
Openalex Percentile: Top 3%
Neural Networks and Applications
7.44
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