DCO-3D: Differentiable Congestion Optimization in 3D ICs
State-of-the-art 3D IC flows fail to consider 3D congestion during earlier stages, leading to excessive use of end-of-flow ECO resources for routability correction that severely degrades full-chip Power, Performance, and Area metrics. We present DCO-3D, a Machine Learning-based routability-aware 3D PD flow that performs early post-route congestion prediction using Siamese Networks and resolves the predicted hotspots using a fully differentiable 3D cell spreading with Graph Neural Network. On 6 industrial designs in a commercial 3nm node, DCO-3D improves Pin-3D, the known best Pin-3D flow, by up to 47.2% in overflow, 86.2% in TNS and 5.1% in power at signoff.
Authors
- Rongjian Liang (ORCID: https://orcid.org/0000-0001-8626-2359)
- Anthony Agnesina (ORCID: https://orcid.org/0000-0003-0393-0230)
- Yi‐Chen Lu (ORCID: https://orcid.org/0000-0003-1481-9167)
- Haoxing Ren (ORCID: https://orcid.org/0000-0003-1028-3860)
- Hao-Hsiang Hsiao (ORCID: https://orcid.org/0000-0003-4865-0654)
- Sung Kyu Lim (ORCID: https://orcid.org/0000-0002-2267-5282)
- Yunpeng Lu (ORCID: https://orcid.org/0000-0003-2493-7853)
- Pruek Vanna-Iampikul (ORCID: https://orcid.org/0000-0002-2897-7142)
Institutions
- Burapha University (TH)
- Georgia Institute of Technology (US)
- Nvidia (United States) (US)
Publication Details
- Published
- 2025-06-22
- DOI
- https://doi.org/10.1109/dac63849.2025.11132448
- Citations
- 3
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 2.19