INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications

Prior GPU-accelerated Static Timing Analysis (GPU-STA) works all struggle to find industrial adoption, primarily because they aim to build standalone timing engines that can never emulate the proprietary delay models used in commercial tools. In this paper, we adopt a different philosophy by presenting INSTA, the first-ever differentiable, statistical GPU-STA engine that achieves unprecedented accuracy and scalability by a one-time initialization from any reference tool, bringing two transformative capabilities to Physical Design (PD): (1) rapid, high-fidelity timing analysis for incremental netlist update, and (2) gradient-based truly-global timing optimization at scale. Notably, INSTA demonstrates a near-perfect 0.999 correlation with an industryleading signoff tool on a 15 -million-pin design in a commercial 3 nm node with runtime under 0.1 seconds. Experimental results showcase INSTA’s capability through three PD applications: (1) serving as a fast evaluator in an industrial gate sizing flow, achieving $\mathbf{2 5 x}$ faster incremental update_timing runtime with almost no accuracy loss; (2) INSTA-Size, a gradient-based gate sizer that achieves up to $\mathbf{1 5 \%}$ better Total Negative Slack (TNS) than the reference signoff engine by sizing $68 \%$ fewer amount of cells; and (3) INSTA-Place, a differentiable timingdriven global placer that outperforms the state-of-the-art net-weighting placer by up to 16% in Half-Perimeter Wirelegnth (HPWL) and 59.4% in TNS on the ICCAD’15 benchmark [15].

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Publication Details

Published
2025-06-22
DOI
https://doi.org/10.1109/dac63849.2025.11132858
Citations
9
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
20.43
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article

INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications

Rongjian Liang, Yi‐Chen Lu, Haoxing Ren, Kishor Kunal et al.
9 citations
Embedded Systems Design Techniques
20.43
article

INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications

Rongjian Liang, Yi‐Chen Lu, Haoxing Ren, Kishor Kunal, Zhixing Guo
article en
9 citations

Abstract

Prior GPU-accelerated Static Timing Analysis (GPU-STA) works all struggle to find industrial adoption, primarily because they aim to build standalone timing engines that can never emulate the proprietary delay models used in commercial tools. In this paper, we adopt a different philosophy by presenting INSTA, the first-ever differentiable, statistical GPU-STA engine that achieves unprecedented accuracy and scalability by a one-time initialization from any reference tool, bringing two transformative capabilities to Physical Design (PD): (1) rapid, high-fidelity timing analysis for incremental netlist update, and (2) gradient-based truly-global timing optimization at scale. Notably, INSTA demonstrates a near-perfect 0.999 correlation with an industryleading signoff tool on a 15 -million-pin design in a commercial 3 nm node with runtime under 0.1 seconds. Experimental results showcase INSTA’s capability through three PD applications: (1) serving as a fast evaluator in an industrial gate sizing flow, achieving $\mathbf{2 5 x}$ faster incremental update_timing runtime with almost no accuracy loss; (2) INSTA-Size, a gradient-based gate sizer that achieves up to $\mathbf{1 5 \%}$ better Total Negative Slack (TNS) than the reference signoff engine by sizing $68 \%$ fewer amount of cells; and (3) INSTA-Place, a differentiable timingdriven global placer that outperforms the state-of-the-art net-weighting placer by up to 16% in Half-Perimeter Wirelegnth (HPWL) and 59.4% in TNS on the ICCAD’15 benchmark [15].

Nvidia (United Kingdom) (GB)
Openalex Percentile: Top 0%
Embedded Systems Design Techniques
20.43
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