GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Coarse-grained reconfigurable architecture (CGRA) has emerged as a promising solution for accelerating computationally intensive applications, particularly in the field of artificial intelligence. One of the primary challenges for CGRA compilers is generating effective mapping results for complex applications within a limited time-frame. This paper presents an enhanced pre-scheduling method that integrates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), along with a corresponding two-stage mapping approach. This combination significantly reduces the search space and accelerates the solution process for mapping problems. Experimental results demonstrate performance improvements ranging from $29.4 \%$ to $406.7 \%$, along with compilation time reductions of up to $1106.8 \times$ compared to existing compilation techniques, as well as excellent scalability.
Authors
- Weiqing Ji (ORCID: https://orcid.org/0009-0009-0328-4241)
- Hailong Yao (ORCID: https://orcid.org/0000-0002-8750-3086)
- Shouyi Yin (ORCID: https://orcid.org/0000-0002-8438-8588)
- Mingyang Kou (ORCID: https://orcid.org/0000-0002-9562-1365)
Institutions
- University of Science and Technology Beijing (CN)
- Tsinghua University (CN)
Publication Details
- Published
- 2025-06-22
- DOI
- https://doi.org/10.1109/dac63849.2025.11132509
- Primary Topic
- Embedded Systems and FPGA Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00