GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs

Coarse-grained reconfigurable architecture (CGRA) has emerged as a promising solution for accelerating computationally intensive applications, particularly in the field of artificial intelligence. One of the primary challenges for CGRA compilers is generating effective mapping results for complex applications within a limited time-frame. This paper presents an enhanced pre-scheduling method that integrates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), along with a corresponding two-stage mapping approach. This combination significantly reduces the search space and accelerates the solution process for mapping problems. Experimental results demonstrate performance improvements ranging from $29.4 \%$ to $406.7 \%$, along with compilation time reductions of up to $1106.8 \times$ compared to existing compilation techniques, as well as excellent scalability.

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Publication Details

Published
2025-06-22
DOI
https://doi.org/10.1109/dac63849.2025.11132509
Primary Topic
Embedded Systems and FPGA Design
Type
article
Field-Weighted Citation Impact
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article

GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs

Weiqing Ji, Hailong Yao, Shouyi Yin, Mingyang Kou
Embedded Systems and FPGA Design
article

GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs

Weiqing Ji, Hailong Yao, Shouyi Yin, Mingyang Kou
article en

Abstract

Coarse-grained reconfigurable architecture (CGRA) has emerged as a promising solution for accelerating computationally intensive applications, particularly in the field of artificial intelligence. One of the primary challenges for CGRA compilers is generating effective mapping results for complex applications within a limited time-frame. This paper presents an enhanced pre-scheduling method that integrates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), along with a corresponding two-stage mapping approach. This combination significantly reduces the search space and accelerates the solution process for mapping problems. Experimental results demonstrate performance improvements ranging from $29.4 \%$ to $406.7 \%$, along with compilation time reductions of up to $1106.8 \times$ compared to existing compilation techniques, as well as excellent scalability.

University of Science and Technology Beijing (CN), Tsinghua University (CN)
Openalex Percentile: Top 69%
Embedded Systems and FPGA Design
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