A Novel Covert Timing Channel for Cloud FPGAs
This paper presents a novel covert timing channel (CTC) that enables a malicious entity to exfiltrate data from a benign cloud FPGA user without requiring dedicated outgoing messages from the cloud FPGA, minimizing the detection risk by both the victim and the cloud service provider. The proposed CTC exploits the handshake signals of the Advanced eXtensible Interface (AXI) protocol and interpacket delay of the Internet to establish the CTC from a cloud FieldProgrammable Gate Array (FPGA) to an off-cloud computer. This paper analyzes the bit-error rate (BER) of the AXI-based CTC under varying conditions and demonstrates its effectiveness in truly enabling remote power analysis attacks on cloud services, such as Amazon Web Services Elastic Compute Cloud (AWS EC2). The proposed CTC achieves a BER as low as 0.01988%.
Authors
- Darshana Jayasinghe (ORCID: https://orcid.org/0000-0003-1910-4048)
- Sri Parameswaran (ORCID: https://orcid.org/0000-0003-0435-9080)
- Hassaan Saadat (ORCID: https://orcid.org/0000-0003-3691-4130)
- Brian Udugama
- Aleksandar Ignjatović (ORCID: https://orcid.org/0000-0001-7427-4934)
Institutions
- The University of Sydney (AU)
- UNSW Sydney (AU)
- Astronomy and Space (AU)
Publication Details
- Published
- 2025-06-22
- DOI
- https://doi.org/10.1109/dac63849.2025.11133099
- Primary Topic
- Physical Unclonable Functions (PUFs) and Hardware Security
- Type
- article
- Field-Weighted Citation Impact
- 0.00