FPGA-based hardware implementation of integrated FEC equalization in bandwidth-efficient IM/DD optical interconnection

An integrated forward error correction (FEC) equalization scheme based on polar decoded decision least mean square (PD-LMS) is proposed and experimentally demonstrated in an intensity modulation direct detection optical 4-level pulse amplitude modulation (PAM4) interconnection system. The error correction capability of polar codes is utilized to iteratively optimize the weight update in the decision-assisted LMS algorithm, achieving simultaneous equalization and FEC reliability enhancement with effective mitigation of inter-symbol interference caused by limited system bandwidth. The experiment of the proposed PD-LMS scheme is illustrated in a 160 Gb/s optical PAM4 interconnection system with a system 3 dB bandwidth of 5 GHz, and its hardware implementation based on a field-programmable gate array (FPGA) platform is also explored. Furthermore, a reliability-driven pruning scheme is introduced to simplify the iterative weight updating in PD-LMS by discarding low-reliability symbols in the FPGA. The results show that the proposed integrated FEC equalization strategy effectively improves the receiver power sensitivity by 1 dB, while achieving a 67% reduction in FPGA hardware computational complexity.