Soft start-up strategy for CLLC resonant converter based on linear active disturbance rejection control

Abstract During the start-up phase, the CLLC resonant converter experiences significant current stress, which poses a major challenge for engineering applications. Frequency-reduction-based soft start-up methods are commonly employed to avoid excessive start-up inrush current and hardware overdesign. However, traditional PI-based frequency reduction soft start-up strategies suffer from prolonged start-up times and poor disturbance rejection capabilities. To address this issue, this study proposes a soft start-up strategy based on linear active disturbance rejection control (LADRC) with a power-law frequency reduction function. The relationship between the input impedance and switching frequency is analyzed in detail, and an optimal frequency modulation function was derived under the given constraints. This ensures a faster output voltage buildup and minimal waveform distortion, while maintaining the soft-switching characteristics of the converter. Finally, both simulation models and experimental prototypes were developed to validate that the proposed strategy effectively reduces current stress and achieved an improved start-up performance.