Abnormal Operation of 6-T SRAM Based on Nanosheet FET Due to Total Ionizing Dose

This study investigates the total ionizing dose (TID) effect on the six-transistor static random access memory (6-T SRAM) consisting of a novel device, a nanosheet field effect transistor (NSFET). Via technology computer-aided design, we simulate the hold, read, and write static noise margin (HSNM, RSNM, and WSNM) degradations by the oxide trap, using stationary simulation. In the stationary simulation, the HSNM and RSNM decrease about 75% and bit flip occurs under the oxide trap conditions, respectively. The voltage stored at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{CH}$ </tex-math></inline-formula> (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{CL}$ </tex-math></inline-formula>) node reduces owing to the leakage current of the pull-down (PD) transistors. The detail degradation mechanism for the SRAM operation (hold/read/write) problems due to the oxide trap is confirmed through the time-dependent simulations. In the read operations, the leakage current at PD transistors causes a bit flip of the CH node. Moreover, the CH node voltage decreases under hold and write operations (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta V_{CH} =15.7$ </tex-math></inline-formula>% and 14%). Significantly, when the adjacent cell (word-line (WL)2) of the target cell (WL1) operates to write data (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{BL}$ </tex-math></inline-formula> down from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{DD}$ </tex-math></inline-formula> to 0), the voltage drop at the target cell (WL1) CH node (decreased by 23.3%) is enhanced under hold operation of the target cell. To mitigate the effects of oxide trap that cause electrical characteristic degradation in NSFET 6-T SRAM, we applied a partial dielectric isolation (PDI) structure that locally deposits an oxide (SiO2) on the bottom of the source/drain (S/D). SRAM cells incorporating the proposed PDI technique demonstrated that variations in SNM caused by oxide trap were suppressed to less than 1% across read, write, and hold operations. Additionally, through time-dependent electrical characteristic analysis, it was confirmed that the potential changes in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{ch}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{cl}$ </tex-math></inline-formula> converge 1% under various operation modes and adjacent cell activation conditions, thereby demonstrating the effective blocking of the effects of oxide trap occurring in the shallow trench isolation (STI) region.