Advanced RF and Mm-Wave Characterization of Local Passivation Layer Compatible With FD-SOI

This work explores the radio frequency (RF) performance of an innovative local passivation layer solution and assesses its compatibility with fully depleted-silicon-on-insulator (FD-SOI) requirements. The solution consists in creating crystalline defects under the buried oxide (BOX) using high-dose He+ implantation combined with thermal annealing. The compatibility of the resulting substrates with FD-SOI requirements was evaluated through RF characterization of coplanar waveguide (CPW) structures using input signals at high frequencies. The trapping efficiency of such a buried defects layer is proved through very low second harmonics power levels below −100 dBm. These harmonics power levels are maintained for frequencies up to 28 GHz and high operating temperatures up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$175~^{\circ }$ </tex-math></inline-formula>C. Besides, crosstalk measurements also confirm the compatibility of helium-based passivation layers for FD-SOI mixed-mode co-integration. Our original approach delivers performances on par with the widely used polycrystalline silicon trap-rich (TR) layers. Its efficient local implementation makes it highly promising for co-integration within FD-SOI or bulk CMOS technologies, where a full-wafer TR layer is not a suitable passivation option.